Semiconductor device fabrication involves using a number of fabrication processes to build a desired device. Generally, a semiconductor device is fabricated on a semiconductor material referred to as a substrate by forming layers or components, selectively patterning formed layers, and selectively implanting dopants into layers and/or the substrate in order to achieve desired operational characteristics.
Several common methods and structures have been used to isolate areas on semiconductor devices and to define the boundaries of certain active regions in the substrate. Such structures that are fabricated in semiconductor devices may include a local oxidation of silicon (LOCOS) region, or a shallow trench isolation (STI) region formed in a substrate as illustrated in prior art FIGS. 2 and 3, respectively. Both LOCOS and STI regions serve to electrically isolate multiple active devices (e.g., transistors) so that they do not interfere with each other's operations. LOCOS and STI are commonly used in CMOS silicon technology.
Generally, an STI region, for example, is formed in/on a device by selectively etching a shallow trench between components or devices, filling the shallow trench with oxide, and then planarizing the device to substantially remove portions of the fill oxide from a surface of the device while leaving the fill oxide within the etched shallow trench.
A typical formation of an STI region employs forming a pad oxide and an etch stop layer prior to etching the shallow trench. The etch stop layer is selectively formed (deposited and patterned) in non-trench regions and is comprised of a material, such as nitride, that is substantially resistant to a planarization process being employed. A trench oxide fill process is then performed that deposits oxide into the shallow trenches followed by the planarization process. A high quality gate oxide layer is then typically grown over active regions using a thermal oxidation process. However, near the edges of the STI or LOCOS regions referred to as bird's-beak areas, a non-uniform local thinning of the oxide growth (reduced oxide growth rate) can occur corresponding to local alterations produced in the silicon crystal lattice structure. This non-uniform gate oxide thinning causes a percentage of the memory cells to lose charge faster than other cells of the array resulting in weak or unreliable transistor devices.
Accordingly, what is needed are systems and methods that mitigate non-uniform gate oxide growth thinning and facilitates more reliable and lower cost memory device fabrication.